High Speed Design - Project
Step by step implementation of high speed design constraint
- Some design rule creation in schematic capture itself.
- Net list transfer to PADS layout.
- Identify High speed design Nets.
- Creation of
- Net classes
- Matched Net Length objects
- Differential Pairs
- Conditional Rules
- Pin - Pairs (if required)
- Using design guides as a reference create a Line Sim document for critical NETS and run pre-layout Signal Integrity simulation with appropriate models for drivers and receivers.
- Based on simulation result determine optimum termination & maximum NET length as well as no. of vias to be used. (For critical Nets like Clocks I use a maximum of 4 vias).
- Component placement keeping simulation results in mind.
- After complete component placement run pre-layout SI analysis using "Manhattan Length".
- Start the routing process in PADS Router.
- Fan-out high speed signals from outer layers to proper strip line layers.
- Route all high speed Nets with proper design constraint based on design rules or simulation results.
- Layer Stack-up creation
- No. of Signal Layers --- Based on total no. of Nets
- No. of Plane Layers --- For distribution of GND and PWR Nets
- Spacing between Plane & Signal Layers --- Depends on Cross-talk tolerance
- Spacing between Plane Layers --- Based on inter-plane capacitance
- Track width in Signal Layers --- Based on trace impedance
- Gap between Signal Layers --- To obtain specific PCB thickness
- Once high speed critical nets are routed power supply routing can begin based on sample layout on data sheets.
- Fan out GND connections for power supply nets. If required separate analog and digital ground.
- Determine proper decoupling @ all voltage rails specially the ones driving single ended wide buses.
- Run Power Integrity simulation for
- dc drop
- impedance vs frequency curve
- simultaneous switching noise
- Route non-critical nets and complete the first iteration of layout.
- Post layout SI, PI and Thermal simulations.
